The present invention relates to an extraction method and an extraction apparatus for extracting variation distributions of characteristics of a semiconductor integrated circuit.
Large scale integrated circuits (LSIs) have increasingly been miniaturized in recent years. For such miniaturized LSIs, variations in layout patterns and arrangement positions of circuit elements or variations in manufacturing processes greatly affect circuit performance. Systematic variations (variations of which causes can be identified using design data) cannot be distinguished from random variations (variations of which factors cannot be identified using design data) in present LSI design environments. Thus, circuits employ worst-case designs, which take into consideration all possible variations and include excessive margins for overcoming the worst conditions. In recent years, LSIs are required to operate at a lower voltage to reduce power consumption and operate at higher speeds. However, circuits employing worst-case designs with excessive margins hinder reduction in power consumption and increase in operation speed. Moreover, it is difficult to provide sufficient design margins for circuits. It is thus desirable to realize designs with reduced margins. For this purpose, it is important that the distribution of variation characteristics in semiconductor integrated circuits be efficiently extracted.
FIG. 1 shows an example of a process for extracting characteristics of a semiconductor integrated circuit in the prior art. First, an electric circuit is generated based on a netlist 1 and a wire model 2, which are prestored in a library (S1). Then, an electric equivalent circuit is generated (S2).
A cell or macro of the electric equivalent circuit is converted into an approximate polynomial expression, and characteristics at target points are simulated using specific inherent values 4 and derating coefficients 5, which are prestored in a cell/macro library 3 (S3). As a result, characteristics of the semiconductor integrated circuit, such as delay time (operation timing), power consumption, and leak current, at the target points are obtained (S4).
The specific inherent values 4 stored for characteristics, such as delay time, power consumption, and leak current of each cell or macro in the cell/macro library 3, are set under the worst condition (worst point), the best condition (best point), and a typical condition. The typical condition is the most frequently appearing condition.
The derating coefficients 5 are set taking into consideration states in which changes of characteristics depending on positions on each cell or macro chip are the largest and a state in which such changes of the characteristics are the smallest.
The simulation in S3 is performed for each of the above conditions including the worst point and the best point. In S4, the characteristics are obtained for each of the above conditions including the worst point and the best point.
The characteristic extraction process described above enables the characteristics at the worst point and the characteristics at the best point to be obtained. However, to obtain variation distributions, the cell/macro library 3 is required to store specific inherent values 4 in accordance with the necessary points. To obtain variation distributions of such characteristics as a delay time, power consumption, and a leak current for each cell or macro, a large number of specific inherent values 4 need to be set, which results in huge burdens. Further, the simulation in S3 needs to be repeated for a number of times corresponding to the number of necessary points.
As a result, the characteristic distributions cannot actually be obtained in the prior art. Thus, only the characteristics at the worst point and the characteristics at the best point are extracted and used in circuit designs.